Design basic logic gates (AND, XOR) using a 2to1 mux. Write a module which will take clk as an input and output a clk divided by 3. Important to note that generated clock needs to be an output of the Flop.
Digital Design Engineer Interview Questions
553 digital design engineer interview questions shared by candidates
RTL coding related questions such as writing a simple FSM.
How can I estimate a new IP complexity and area without having any specific details yet?
design a trafffic light controller
Digital electronics questions, C programming questions, Combinational and sequential logic.
I was asked to write the RTL code for an asynchronous receiver in Verilog
basic mosfet circuitry questions, got to know
Had to fill in a truth table of a multiplexer
What it a flip flop and what does it do
hold setup time, metastabilità - clock divider - filtro fir - floating point
Viewing 371 - 380 interview questions