FIFO size calculation, CPU bus interface questions
Digital Design Engineer Interview Questions
553 digital design engineer interview questions shared by candidates
Ask to make an inverter from both CMOS and BJT. Also ask advantages and disadvantages of each.
setup time,hold time timming analysis , vlsi design flow
More questions in CDC, Constraints used in SDC and about Primetime report.
Two or Three basic questions on power speed optimization in static CMOS
Which parameters are to be considered to choose value of the bypass capacitor
Asynchronous fifos, critical path timing, formal verification, clock gating, hight vt vs low vt
DDR2 initialization engine synthesis issues (from my resume).
Was asked about basic protocols for PCIE. Basic questions on CDC. Types of violations that the CDC tools complain - eg: no_sync, combi logic before double sync, multi bit double syncing, re-convergence etc. Code async reset FF and sync reset FF. What are the dis/advantages of one over the other.
For aptitude, the interviewer asked me roughly how many trees I pass by from my house to the campus.
Viewing 171 - 180 interview questions