Sequential timing setup and hold times definition and understanding
Digital Design Engineer Interview Questions
553 digital design engineer interview questions shared by candidates
hardware to multiply 8 bit number by 9 without multiplier
Clock domain crossings in cases where very fast sending signals arriving at a much slower clock domain. How to capture without losing any incoming signal event into the slow clock domain? No idea as to how frequent or how long incoming events appear.
What does this circuit do?
If you connect both ends of a wire will it read characteristics impedance
Question related to thesis work
There was a badly described rtl (flip-flop) without clk in the sensivity list. They asked if it was synthesizable.
Q1. Tell me about yourself ?
Timing analysis on a given digital circuit. How to pipeline the given design.
Basic Digital Design Skill Relocation Package
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