basic digital design questions, static timing analysis and also verification using system verilog.
Digital Design Engineer Interview Questions
553 digital design engineer interview questions shared by candidates
Round 1:- Logic Families, Mux, Demux, In CMOS circuits, which among tphl and tplh is longer? And why? Divide-by-3 counter, Round 2:- (after a wait of the futile 4 hours) Significance of 'reset' signal in digital circuits Given a step input to a low pass filter, high pass filter and band pass filter respectively, what do you expect the output to look like? Dissimilate a square wave into its harmonics (this question because I had mentioned signal processing projects in my resume) Now a days we have a large number of cells in logic blocks? What do you think is the approach to detect an error in such a case?
What is setup time and hold time?
Enlist the relative and absolute timing parameters of an inverter?
Complete digital design like sequential circuits and combinational circuit
Memory organization - build 64kb x 64-bit memory using (1.) 32kb x 16 bit and (2.) 16kb x 64bits.
Design FSM for an elevator going between Floor 1 and Floor 2 with buttons inside the elevator to go to the floors and sensors at each floor to sense whether the elevator has reached the floor.
logic design question setip hold time
scripting language code
White-board diagram of a block with one input pin (+ clock), and one output pin. The input is a serial stream of data. The output =1 whenever the pattern "0110" has been seen on the serial data. Everything is synchronous to the clock input. Write the Verilog. Given the shortened time constraint for the interview, diagram the design solution. In addition to what you come up with, write a bubble diagram for an FSM solution.
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