I was asked to write the RTL code for an asynchronous receiver in Verilog
Digital Asic Design Engineer Interview Questions
39 digital asic design engineer interview questions shared by candidates
Had to fill in a truth table of a multiplexer
What it a flip flop and what does it do
Clock domain crossings and reset domain crossings
Wie funktionieren Flip Flops? Wie funktioniert SerDes?
What is a fpga and what is a lookup table?
Some code test. Some system knowledge test.
Es war ein technisches Vorstellungsgespräch, bei dem vor allem Fragen zum Lebenslauf gestellt wurden,
What greek philosopher didn't write any of his works?
Verilog code for shift register.
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