They asked detailed questions about memory and interconnect design in advanced systems. They also gave me a small assignment which I had to do online.
Design Verification Interview Questions
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masters project in in depth in terms of technicalities
About digital electronics for VLSI domain
Why modport is used? What is polymorphism? What is deep copying ? what is inheritence? Why we are writing interface? Different Phases in UVM? Which phase are task and which are functions?
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
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My projects which was relevant to job role
Asked me questions on Tessent tool
My experience was bad in 2 rounds otherwise good in other 3 rounds.
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