State machines, VHDL, basic logic and design.
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
Technical Screening: Q: I was asked about basic programming questions like Leet Code (easy) but mostly based on array, hash-maps, strings and also resume discussion Full-Panel: Q: SystemVerilog constraints, fork-join, mailbox and semaphores based questions Q: Was asked to write scoreboard for a Asynchronous FIFO Q: Monitor and scoreboard code for an AXI write transaction (project based) Q: Resume based discussions Q: Some basic programming problems in language of preference
What is setup and hold time What is skew What is synchronous and asynchronous reset
Design a FSM to detect a certain sequence of numbers.
set up time, hold time
-Questions about cache coherency -Basic Verilog Questions -Questions about c++ and traversing trees
Design an FSM for an elevator, different kinds of coverage, describe some RTL bugs you found in your current role, describe UVM testbench, how are sequences and drivers connected
FIFO depth, and ASYNC FIFO test plan
como voce se ve daqui 19 anos
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