Circuit design, Flip flap, Boolean logic, control logical gates etc
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
Basic questions related to System Verilog and UVM
write a Verilog code of FIFO design
Tomasulo algorithm and resume project/ experience
I Am Trained Asic Verification Engineer.. They Ask Some Digital Electronics Questions.. They Will Judge You On Basis Of Your Digital Electronics Knowledge .. Even They Didn't Ask Me A Single Question From Verilog, System Verilog And UVM ... Which I Know Batter .. I AM Not Good In Digital Electronics
Design a Neural Network for a system.
1. Memory design and block diagram 2.Verilog programming 3.C++ (oops concepts) 4.SV & UVM components
Difference between 8085MP and 8086
All the questions related to sv, uvm, verilog
Setup and Hold time analysis Counter design Sequence detector Verilog questions
Viewing 191 - 200 interview questions