functional, code coverage ,priority encoder explanation, SV
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
Calculate bandwidth for 16 bit data bus, data rate: 50 MHz and only 25% of time.
Detect that N numbers have arrived based on a control signal. Flag the average of all the N numbers once the N-numbers have arrived.
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
Setup-Hold timing inter-relationship question, framed by way of max frequency of operation
Provided a waveform and asked to design a circuit for that.
1. Some simple random stimulus with specified constraints
Cache
Sequence detecting FSM, coding it in Verilog
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