How to solve CDC problems
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
I had all my questions related to my job.
About the things in Resume
What is setup time/ hold time violation ? How are they related to the frequency.
Array, system verilog,uvm, mailbox Queue fifo configdb etc
Explaining the concepts of setup time and hold time in digital chip design
Wie funktionieren Flip Flops? Wie funktioniert SerDes?
Design a state machine for an elevator with buttons 1, 2, 3, 4, up, down
There were three technical round in that they ask whatever protocol you know or mention in your resume. They ask about STA, CDC, Process of Vivado RTL flow. They also ask logical riddle to check your logical thinking.
What is the one thing that you are proud of yourself during the learning process ?
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