I was asked to write the RTL code for an asynchronous receiver in Verilog
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
Q. Design a 16X1 MUX using 2X1 mux, How many of need? Q. Many More.
Had to fill in a truth table of a multiplexer
What it a flip flop and what does it do
Describe your best project.
Suppose we want to build a 16x16 multiplier, but we only have 4x4 multipliers and adders. You can use as many adders as you want, what's the minimum number of 4x4 multiplier do we need to build 16x16 multiplier?
some basic concepts for FSM
very detailed clock divided by three
how to solve clock skew, detailed process
Standard design questions.
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