No difficult questions
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
Setup and hold time for circuits
1. what is the max freq of a given circuit.(setup and hold analysis related) 2. one question was related to stuck at fault. we need to find out the input test pattern in order to detect the stuck at fault of given circuit. 3. IN1?A:IN2?B:IN3?C:1'b0 How many 2:1 mux are required to implement this? 4 one question was related to FIFO Depth calculation. 5. In a given circuit to meet timing how many no of re timing flops need to be inserted?(you should be clear with setup analysis) 6. Questions were related to transistor sizing and cache memory hit and miss ratio. 7. One puzzle was also asked of Annual function and van related(don't remember exactly. :p)
AND & OR gate from 2-1 MUX.
Describe an application where you would use a latch?
Design a two bit single cycle multiplier Write a code to check if it is palindrome or not? FSM to count the series of 1's. Single bit input per clk. Series of 1's must start and end with a 0
implement a counter, analyze signal diagram
What will be the multicycle be for 0 cycle paths?
Design some circuit using 2x1 mux only. Design a CMOS and gate
How do you divide clock
Viewing 161 - 170 interview questions