How to design an Accumulator. How to generate ramp signal in verilog. What are start and stop bits. Min. delay and Max. delay.
Verification Interview Questions
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Body effect CMOS working
UVM phases and uses are a must.
Offered coding questions on the spot at the last ten minutes of the interview.
What is ASIC Design flow?
Whatever you have worked on, Specialisation ,SV and UVM. Prepare well whatever you have mentioned in your resume.
Digital Electronics:- FSM, Register, Flip flop, MUX. Verilog:- write program for FSM, clock generator, mux. SystemVerilog:- programming question based on randomisation. UVM:- write code for driver sequencer ,Tlm ports.
Basics and some basic circuit verification
Tell me about yourself?
explain ASIC flow
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