Draw an AND gate using transistors.
Verification Interview Questions
3,649 verification interview questions shared by candidates
What are the limitations of current design methodologies?
Design a digital circuit that on every third cycle calculates the average between the first and the second posedge and write it in verilog
UVM and verification questions mainly
1) Tell me about yourself 2) Tell me about the projects on your resume
-General digital flow design -General UVM verification questions
1.difference between dynamic,static ,short circuit power diddipation ,where and how it happens ,how to reduce them 2. power reduction technoques at logic and architectute level 3. verilog
UVM Concepts and Work Experience of previous project
How we can integrate agents without them generating stimulus
During the interview, I was asked questions related to my experiences in the field. Setup hold, clock multiple. Specifically, discussions centered around the technical aspects of clock multiple, as well as an exploration of my work experiences and the responsibilities associated with my role.
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