1. Write a Verilog code to generate a clock signal at a certain frequency. (a lot of Verilog basic problems) 2. draw a CMOS logic gate 3. Why do you want to be a DV person? 4. What is the most interesting class you took? 5. Other real-life related engineering problems (related to SNR)
Are you a team player?
There's a circuit diagram of a pulse generator: a 2-input NAND gate with one of the inputs three inverters downstream from the other input, with some propagation delay for each inverter. Given the timing diagram of the input, what does the output look like?
A question of logic - very simple
AXI protocol and SV and UVM
Project overview, tech stack, Ai/ml
uvm tb structure, missing code completion, pointing to errors. factory overwrites etc.
C++ - classes and virtual functions, abstract.
resume based
Difference between copy/clone methods in UVM
Viewing 851 - 860 interview questions