UVM phases and uses are a must.
Verification Engineer Interview Questions
2,558 verification engineer interview questions shared by candidates
Offered coding questions on the spot at the last ten minutes of the interview.
What is ASIC Design flow?
Whatever you have worked on, Specialisation ,SV and UVM. Prepare well whatever you have mentioned in your resume.
Digital Electronics:- FSM, Register, Flip flop, MUX. Verilog:- write program for FSM, clock generator, mux. SystemVerilog:- programming question based on randomisation. UVM:- write code for driver sequencer ,Tlm ports.
Basics and some basic circuit verification
What is your weakest quality?
How will you initiate a verification?
some puzzles like 25 horse running and select first 5. SOme questions on page tables and memory.
Describe loading speed
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