Technical questions and some logical Questions
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
Give a situation when your input made a difference in a project.
How much of an improvement did your input make compared to the original decision? OR If there was compromises made, was the performance better or worse?
They asked me to sort an array with an specific condition, without sorting
I didn't experience anything that was not expected in some way.
Define verilog ,systemverilog. Memory /cache
Write a function that creates a randomized array of integers from 1 to 100, each number appearing once.
SV, UVM and Digital Electronics Questions.
Tech Interview: Basic Questions like Lifo Fifo, Stack Queues, Logic Gates HR Interview: About myself, Job expectation, Other Interests
Uvm phases and explain them
Viewing 2361 - 2370 interview questions