Verification Engineer Interview Questions

2,558 verification engineer interview questions shared by candidates

During the interview, I was asked several technical questions that tested both my low-level and high-level understanding. One of the questions required me to write multiplication code in assembly, which challenged my ability to think at the instruction level. Another question focused on the operation of moxies, testing my knowledge of architectural or system-level behavior. Additionally, I was asked a question related to verification, where I needed to demonstrate my understanding of validation methodologies and how to ensure the correctness of a design. These questions provided a well-rounded assessment of my skills.
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Verification Engineer

Interviewed at NVIDIA

4.4
Jun 27, 2025

During the interview, I was asked several technical questions that tested both my low-level and high-level understanding. One of the questions required me to write multiplication code in assembly, which challenged my ability to think at the instruction level. Another question focused on the operation of moxies, testing my knowledge of architectural or system-level behavior. Additionally, I was asked a question related to verification, where I needed to demonstrate my understanding of validation methodologies and how to ensure the correctness of a design. These questions provided a well-rounded assessment of my skills.

All the interviewers are Indians and were really nice. I had a really good conversation each interview is about an hour. Everyone had a set of questions prepared and asking me to solve. 1. Full SV - fork join_none, virutal functions, $cast, static variable, Cache size - direct mapping, MESI FSM, constarints, parity check - post randomize 2. STA - hold violations, max freq, FIFO depth, metasibility 3. DUT - muti master muti slave bridge verification - draw the env and testcases, AXI signals 4. UVM - phases, AXI why not APB?, AXI lite vs. AXI 3.0, Driver code, coverage class and do cross coverage. 5. HR -> about team work, resources you used in a project, set back you faced. Explained most employee benefits, applying for H1B and green card, etc
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ASIC Design Verification Engineer

Interviewed at Qualcomm

3.8
Jan 28, 2021

All the interviewers are Indians and were really nice. I had a really good conversation each interview is about an hour. Everyone had a set of questions prepared and asking me to solve. 1. Full SV - fork join_none, virutal functions, $cast, static variable, Cache size - direct mapping, MESI FSM, constarints, parity check - post randomize 2. STA - hold violations, max freq, FIFO depth, metasibility 3. DUT - muti master muti slave bridge verification - draw the env and testcases, AXI signals 4. UVM - phases, AXI why not APB?, AXI lite vs. AXI 3.0, Driver code, coverage class and do cross coverage. 5. HR -> about team work, resources you used in a project, set back you faced. Explained most employee benefits, applying for H1B and green card, etc

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