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Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
write code which returns error if we got 10 packets within 10 seconds
Uvm phasing process, different phases in uvm
1. Describe verification process of some modules 2. Describe typical test environment (monitor, driver etc) 3. Some common SystemVerilog problems and questions
First round: 1) Introduction on your experience, the job profile requirement and your motivation. DIscussion our application and CV. Second Round: 1) Technical questions on the projects you worked on. This will be in details. Both simulation based ( SV/UVM) and formal methods were discussed. Third round (HR): 1) very generic HR questions like, tell me about your self, your strengths/weakness, motivation to join Synopsys, what your team will say about you . describe a conflicting situation you handled, how do you keep your team motivated, salary expectations and personal situation etc.
Tell us more about your work at "A." How would you verify something? How would you go about writing a protocol and timeless for a project?
Can you tell me your years of experience in ____ ?
Verify a protocol and tell checkers
What did you do in the current position ?
What projects did you do in this domain? Explain.
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