Write a function that checks if a string has valid parentheses
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
write a C program for fibonacci series, some questions on FSM
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
Difference between verilog and sv.? Basic interface questions.
Why Qualcomm?
question around the system verilog ,verification methodology.
FSM for sequence detector. Verification environment. Verilog programming.
How to set config_cb from lower to higher hierarchy
OOPs questions and also ASIC and Verfication based questions
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