Difference between verilog and sv.? Basic interface questions.
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
Asked about project details and uvm sv concepts
How will you verify this circuit ? ( A black box)
Previous project based questions Work Motivations Basic Engineering questions like Wireless technologies, SMPS, Power consumption etc
1. Constraint random, assertions, UVM env 2. OOPS concept 3. Coverage, python scripting 4. Verilog and digital logic
FSM for sequence detector. Verification environment. Verilog programming.
How to set config_cb from lower to higher hierarchy
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
OOPs questions and also ASIC and Verfication based questions
Is program counter a physical memory address or a virtual address?
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