* job experience and roles * how do u verify a scheduler * A block has inputs of network pkts and buffers/pipelines them through an RTL. RTL has counters which will tell how many packets are sent. How to verify? (Counters Read => count. Write => clear) How to verify counts? what cases will u test? * Given a sys verilog code for a memory model and asked to implement read/write/move functions and write checks
MEmory related coding and DRAM related questions
static timing analysis
network theory
In UVM, what if we register a component in object utils.
Write a MATLAB code to simulate the voltage response of the previous circuit.
Define verilog ,systemverilog. Memory /cache
no really difficult questions
FPGA Verification engineers need SystemVerilog and UVM experience
design and verify a module
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