How are you generating clock in verilog, difference between fork-join and begin-end
Verification Engineer Interview Questions
2,562 verification engineer interview questions shared by candidates
FSM diagram of sequence detector and write verilog code
Difference between strobe and monitor?
System verilog and uvm related questions
How many phases are in Uvm and what is the order of execution
What is outstanding and out of order transaction
Write verilog code,difference between gate and latch,demonstrate difference between asynchronous and synchronous reset using waveform,what is a gitch
Write a SV code for (given) circuit
in one on one they asked what is duality theorem,inheritance nd mckinsley method
why do I apply this position, previous coding experience
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