related to projects done before. but none of the direct questions.
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
1. difference between flip flop and latch. 2. difference between blocking and non blocking. 3. System Verilog verification architecture. 4. difference between verilog and system verilog.
SEL Value; questions about my background; verification process.
4-5 general hdl design questions, fast paced
Draw diagram of jtag logic. Can you use a tdr instead of ijtag?
Two leetcode style questions on arrays, asked to find the output of a SV code and writing Driver class for an SPI with single master and multiple slave.
This was an entry level position. Basic questions were asked about FIFOs and metastability. Then I was asked to code an RTL Design for an Ethernet cable. Had to dissect packets of data and extract the payload while discarding everything else.
It takes 30 minutes found question like halfadder , bitwise operation , function call related problems in the verilog
Selenium commands TestNG
Q. Write assertion on a stated scenario Q. Questions on code and functional coverage
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