Verilog program for d flipflop
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
1. about asynchronous feedback logic. I did not know asynchronous circuits.
Config_db questions.
70% of simple aptitude, digital, verilog, system verilog and UVM descriptive questions. and some moderate and in depth questions.
For a sequence detector, write the code in UVM.
What're the phases of UVM?
OOP Concepts
Difference between true and false dependencies
About my experiences and what I can bring to the company
Array, system verilog,uvm, mailbox Queue fifo configdb etc
Viewing 1821 - 1830 interview questions