On projects and sv uvm based Protocol knowledge on what we mentioned in resume
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
Asked me to tell about myself, past work I’ve done, what do I expect from my new team, manager, etc.
What would I do if there is a conflict with a team member. What I have done in my current job.
System verilog constraints,c programs and data structures
factorial in regular and recursive way
Questions on interface, clocking blocks, assertions, uvm, X propagation.
SystemVerilog assertion and functional coverage coding.
Dont remember much but mostly code deep dives and situational questions related to work.
Describe tokenizing concepts?
Didn't attend the interview
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