Polymorphism, config db.
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
coding a uvm_driver and interface based on a clk, req, ack, signal set.
This will be based on your resume they will tell you on which topic they are going to ask when scheduling the interview
Questions on constraints and assertions
Some in depth questions on digital design
Designing multiple Gates or some basic logic using Multiplexers. Draw state Diagram & verilog code for 1010 sequence detector.
Questions were from device physics, Analog Design basics like a current mirror, charge pump, LC-VCO, lumped components based circuits, Analog layout, PVT variations effects on basic analog blocks, so on, mostly from my previous work experience.
Setup and hold constraints in a circuit
Design issues in asynchronous FIFO
What will you do in case one of the projects gets a customer complaint? How will you handle it - giving feedback to the project members and making sure that the same problem never gets repeated in future?
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