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Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
hardware questions like division by 3 FSM, linked list, c function and you should say what is the output, how you'd solve concurrency of 2 cpu trying to change same register value
Mainly hardware based questions during interview
Basic questions regarding embedded systems, signal processing and wireless communication.
Between timing and quality what would you prefer
Previous projects
UVM related, SV, RAL models etc Based on your resume - protocols
Q: Can you explain the difference between blocking and non-blocking assignments in SystemVerilog? Q: How would you verify a FIFO design? Q: What is a virtual interface and how do you use it in UVM? Q: How do you handle back-to-back transactions in a UVM sequence? Q: How do you debug a failing assertion in simulation?
what is mailbox why we don't use queue instead of mailbox. what is polymorphism and their uses. what is diff bw trsanction and transfer wrt axi.
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