define tlm fifo's?
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Digital and SV ,UVM verilog basis
Basic sv and uvm and some digital verilog.
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
1. Overall was on project 2. UVM methodologies and SV 3. Have been asked on logical reasoning 4. Queries on verilog, RTL coding were asked. 5. OOPS based concepts ,Polymorphism, Inheritance, Arrays methods, stacks ,Queues, Multidimensional arrays ,Vectors
- code coverage: types, why, how to collect, analysis. Functional coverage: why, how, analysis.
- structure of a typical verification environment, explain each block. Verification closure process. Top/chip level verification, block level reuse techniques.
- problem solving: 1) write systemverilog properties to verify a given, simple protocol. 2) compute the optimal FIFO depth given the in and out timing specs. 3) Write the RTL for a FSM then synthesize it.
Mostly about verilog, Problem solving skills
Verilog based basic questions , SV and UVM questions
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