Computer Architecture, Logic design, validation, software, behavioral.
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Not really difficult, jut really technical
Was tested on computer architecture, pipeline, hazards, fsm, uvm basics, writing system verilog test benches for resume projects
find the minimal number of semi-binary numbers that sum up to a given number. semi-binary is an integer that is composed only by the digits 1 and 0.
about projects, verification methodologies, UVM, System Verilog testbench, Computer Arch, MESI protocol, Cache UVM testbench components, constructs Digital Design questions FSM types and differences Divided by 2 clock design and code Basic Gate level designs
Round 1: 1. What is Functional Verification? Round 2: 1. What is the difference between Verilog and System Verilog? 2. What is the difference between Blocking and Non-Blocking assignment? 3. What is an FSM 4. Mealy and Moore machine 5. What is the difference between synchronous and asynchronous design? 6. Verification using test environment 7. UVM testbench 8. Synthesis design model 9. Critical path 10. Setup time and Hold time 11. Metastable state And some more verification related stuff
They asked about mu uvm design verification project
I can't remember much, but one question was on Finite State Machine for Traffic Lifgt control.
The first interview related to the introduction about both parties and a personality check of the candidate
Black-box vs white box testing, techniques used while verifying designs, system verilog constructs related to verification, UVM OVM etc
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