Generate a 2Ghz clock and code the FSM (The one with the asynchronous reset) in verilog.
Verification Engineer Interview Questions
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What did you do at your previous co-op employer?
Difference between blocking and non- blocking
what are main differences between UVM monitor and UVM driver classes?
FIFO depth in the design
Fifo Depth Calculation
latch-up, filters, Nand gate using CMOS, mux implementation.
What is your weakness and strength
A shunt voltage regulator made up of a voltage divider and a reverse biased zener diode. Plot the output voltage against the input.
Create an f/3 frequency counter at 50% duty cycle with an input clock frequency f
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