- Constraints for Randomization of variables - Functional Coverage for the variables - Theory of SV and UVM concepts in depth -> factory, config db , - Was asked to code a driver for a given interface.
Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
How do you handle stress situation
Given an async fifo, tell the testplan --> complicated fifo with lot of requirements..(writes are done by 3 masters. there is an arbiter).
4. explain interrupt handling, and various scenarios
7. hr questions
If you have a DC power supply in series with a 1k resistor and a 6k resistor, give the equation that described the voltage across the 6k resistor. Switch the 6k resistor for an inductor, what is the voltage across the inductor? Switch the inductor for a capacitor, what is the voltage across the 1k resistor? Change de the 1k resistor for a cap identical to the other one, what is the voltage drop across each cap? Change one of the caps to make it double the capacity of the other one, what is the voltage drop across each cap?
What did you do in your last job?
SystemVerilog assertion and functional coverage coding.
describe UVM Phases and difference bet run phase and main phase
Why did you apply for the verification role.
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