what is metastable state in flipflop? what tool you have use for synthesis? what is setup time and hold time? how you can solve setup and hold violations?
Rtl Design Interview Questions
212 rtl design interview questions shared by candidates
Draw an OoO core and describe how it works
basic in Electronics side and digital electronics. he ask HDL language, clock domain crossing,DFT questions,Automatic test pattern generator and Basic FPGA questions.
About Digital Electronics, Verilog, C.
1st round - basic of digital electronics , basic of verilog , RTL basics , frequency divider fkt, flip flops and latches all the basic things about VLSI 2nd round- some basic technical discussion and about my project work
Basic Digital Design Questions
Difference b/w SRam DRAm
He asked to write code Verilog FSM
One thing that you did differently in a project compared to every one else in class
One of the tough questions was that you are given some data table for two communicating blocks . you are supposed to calculate latency and bandwidth. struggled to find out the band width.
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