Cache coherency, reorder buffer, memory hierarchy, register renaming, data hazards.
Rtl Design Interview Questions
212 rtl design interview questions shared by candidates
Mainly related to best techniques for hardware design and algorithms
Do latches have Metastability?
What is the difference between latch and flop?
Based on memories, digital design, Verilog coding
What is your productive skill
Know the 5 stage pipeline well
Explain each state in a mesi protocol.
Software (OOP, efficiency, data structures), Computer Architecture (cache coherency, pipelining), Logic (k maps, simplifying boolean expressions), and Verification (coverage, how to test, previous experience)
Difference bw asynchronous and synchronous circuits Propagation delay Static and dynamic delay
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