Why double sampling works?
Rtl Design Interview Questions
212 rtl design interview questions shared by candidates
Verilog: Difference btw sequantial and combinational logic. Difference btw blocking and non-blocking assignment.
Q: Setup and hold time questions based on the circuit shown.
Q: Define different pipeline hazards.
Protocol specific questions, basics of SV and UVM constructs
projects related on cv, low power
Verilog coding rounds - FIFO, arbiters, CDC code, fibonacci sequence, simple logic design codes.
Resume based questions - DMA design, cache, source synchronous protocol, AXI protocol, fabric related questions etc.
Processor peripherals, CSR related questions such as R1C, R1T etc registers, debug, trace and performance event monitoring.
What is metastability? clock domain Crossing questions.
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