Questions on FSM, STA, FPGA, Verilog Basics, SV Basics,
Rtl Design Engineer Interview Questions
185 rtl design engineer interview questions shared by candidates
All the basics of digital and verilog
Cache coherency, fifo design , clock , Perl scripts,
They given input frequency and output frequency and told us to draw output waveform for clock divider in verilog
Design freq divider, counter, convert 1 design to another design
No difficult questions . basics of digital electronics
draw hald adder, logice gates, multiplex, verilog
based on Verilog Counters and timing
There really isn't anything unexpected, the HR questions are also really standard and no tricky question like your weakness or how to deal with someone who is hard to work with.
General system design, general CDC questions, questions on experiences,
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