whats the ad and disad of using large cache and small cache
Ingeniero Asic Interview Questions
1,076 ingeniero asic interview questions shared by candidates
Clock skew? Good or bad for a circuit with 2 flops and combinational logic in between.
There are two questions, one is about FSM, you should design a FSM with 5 bit, its function is to counter the even number of 0 or 1, e.g. 2, 4, 6....
What will happen if a default case is not used in a case statement?
Check the awareness of applying pre and post randomization in variables in uvm_object.
5/6 interviewers asked about past work experience, design problems, and analysis of circuits. One interviewer asked general get-to-know you questions.
Fifo functionality and verilog code to write
the questions that were asked were basic digital design was asked to design a mod 10 counter using t flip flop
About my understanding of layout tools, the environment and fluency on the design flow.
1: Asked me about my resume. Mainly about the DDR2 memory controller on my resume. 2: Asked me about FPGA.
Viewing 81 - 90 interview questions
See Interview Questions for Similar Jobs
Ingeniero De Diseño Circuito IntegradoIngeniero Diseño De Sistemas ElectricosIngeniero De Diseño AeroespacialIngeniero Eléctrico De Diseño De TransformadoresTecnología De Ingeniería MecánicaTecnologo De Ingeniería MecánicaIngeniería MecánicaIngeniero De Diseño AsicIngeniero De Diseño De Hardware EléctricoIngeniero De Diseño Electrónico De PotenciaIngeniero VlsiIngeniero De Diseño De Hardware AsicIngeniero De Hardware EléctricoIngeniero Eléctrico En Electrónica De PotenciaIngeniero De Diseño Ic SéniorIngeniero DftIngeniero De Diseño LógicoIngeniero De Diseño Físico Soc