Design OR gate using MUX
Ingeniero Asic Interview Questions
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Data Structures: Linked Lists , Binary Search Tree Concept and Complexity. Hash Tables in C++/Python. C++: Private vs Public Pass by Value vs Pass by Reference Pointer vs Reference Computer Architecture: Pipelining What is Cache & Cache Performance (Hardware & Software) Cache Architecture Virtual Adress Address Translation TLB Explain your Class/Internship Project
they focused a lot on OOP, which is unexpected given the title that I applied.
How to bring a signal from one clock domain to another
how to design the next generation product with 2 times of throughput?
choose right cache strategy
What is a NAND gate
What are CDC and metastability?
Creating a unique list from a list with repeats
Write some codes to explain how to design asynchronous FIFO.
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