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Be ready to be asked what the output of a circuit would look like if the input was ___. exam had 3 circuits, 2 of which I didn't even have a chance to do. Questions were really advanced, and even the manager said it's a really tough exam.
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Hardware Development Engineer I

Interviewed at Fortinet

3.8★
Nov 2, 2016

Be ready to be asked what the output of a circuit would look like if the input was ___. exam had 3 circuits, 2 of which I didn't even have a chance to do. Questions were really advanced, and even the manager said it's a really tough exam.

1.)They gave an input data stream A0, A1, A2, A3… and asked me to design a circuit such that it calculates the sum of the previous two inputs, one clock cycle later. For example: when A2 arrives at that clock cycle, the output should be A0 + A1. When A3 arrives, the output should be A1 + A2. Then they modified the question and asked for the cumulative sum of all previous inputs: For example: when A2 arrives, the output should be A0 + A1. When A3 arrives, the output should be A0 + A1 + A2. 2.)They asked me about 2-bit comparators and the design process. Then they extended the problem: using external logic gates, design a 2-bit comparator assuming you are provided with multiple 1-bit comparators. The comparator has two inputs and three outputs (A > B, A = B, A < B). For example, consider two 1-bit comparators for the MSB and LSB. If the MSB comparator gives A > B = 1, then what should we do for the LSB using logic gates? Similarly, what happens when A > B = 0, and so on for all three cases (A > B, A = B, A < B).
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Hardware Engineer

Interviewed at Texas Instruments

3.8★
Sep 16, 2025

1.)They gave an input data stream A0, A1, A2, A3… and asked me to design a circuit such that it calculates the sum of the previous two inputs, one clock cycle later. For example: when A2 arrives at that clock cycle, the output should be A0 + A1. When A3 arrives, the output should be A1 + A2. Then they modified the question and asked for the cumulative sum of all previous inputs: For example: when A2 arrives, the output should be A0 + A1. When A3 arrives, the output should be A0 + A1 + A2. 2.)They asked me about 2-bit comparators and the design process. Then they extended the problem: using external logic gates, design a 2-bit comparator assuming you are provided with multiple 1-bit comparators. The comparator has two inputs and three outputs (A > B, A = B, A < B). For example, consider two 1-bit comparators for the MSB and LSB. If the MSB comparator gives A > B = 1, then what should we do for the LSB using logic gates? Similarly, what happens when A > B = 0, and so on for all three cases (A > B, A = B, A < B).

This is from the case study questionnaire: You are in a phone call with a sales team member and the customer. The customer is asking for a system that integrates an i7 processor and a graphics card. The graphics card need to have at least 3 video outputs and be of the nVidia GTX 750 performance level. The customer is primarily looking for a system that meets his functional needs – he is open to either fanned or fanless solution. What options would you present to the customer?
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Hardware Applications Engineer

Interviewed at OnLogic

4★
Sep 24, 2017

This is from the case study questionnaire: You are in a phone call with a sales team member and the customer. The customer is asking for a system that integrates an i7 processor and a graphics card. The graphics card need to have at least 3 video outputs and be of the nVidia GTX 750 performance level. The customer is primarily looking for a system that meets his functional needs – he is open to either fanned or fanless solution. What options would you present to the customer?

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