basic questions about FPGA
Fpga Engineer Interview Questions
542 fpga engineer interview questions shared by candidates
implement a box that have an input data (1 bit) that has pulses of 1 clock width (clk_in) and one output data that has a different clock rate (clk_out: faster/smaller), and the data should go out for only one clock pulse (in clk_out). what are the limitations in rate of such box. note that you can use only FPGA existing components
A question on FIFO depth and Constrained Random Verification
You have a pen and a whiteboard, how would you test it?
What are the two different ways of writing VHDL?
Design a decoder for a particular stream
There really wasn't any difficult questions
What is difference between verification and validation
what is my technical background?
What kind of team do you manage?
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