In the screening call: quetions about your background and personal projects, then 2/3 questions on digital design basics. Questions about Verilog HDL, logic synthesis, timing constraints, metastability, finite state machines, basics of verifications, testbenches, logic gates at transistor level, application of De Morgan law, small problem on digital circuits (counters, clock dividers, FSMs).
Previous experience and coding part
Easy questions like write DFF etc.
You have a device connected with a I2C bus. You send the data to the FIFO inside this device. How can you let the master know about FIFO overflow?
Questions related to CDC and Verilog/VHDL. one behavioral question. Questions from the resume.
Reverse an array in-place
Delay the bus signal with BRAM.
OOP concept . like drawing problem. design object to do that.
You are just asked for technical questions without any behavioral questions.
blocking, non blocking. timing analysis, FF, verilog...
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