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6,856 engineer i interview questions shared by candidates

Interview process was quite awkward, people sitting inside doesn't have any patience to listen the answers completely and neither knowledgeable in the area of expertise. The interview was more for a guy who is a book worm and recites the text book parameters like a school kid.
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Senior R&D Engineer I

Interviewed at Synopsys

3.8★
Jan 31, 2013

Interview process was quite awkward, people sitting inside doesn't have any patience to listen the answers completely and neither knowledgeable in the area of expertise. The interview was more for a guy who is a book worm and recites the text book parameters like a school kid.

I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.
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Application Engineer I

Interviewed at Synopsys

3.8★
Oct 7, 2022

I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.

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