Name one time you had to have a difficult conversation and how you handled it.
Design Verification Interview Questions
1,113 design verification interview questions shared by candidates
How do you convince design team that a DUT has been thoroughly verified?
What are the profits range of additional circuit implemented to power saver?
What is the name of the button on the oscilloscope used to zoom into the signal.
A rudimentary sort of #s in PERL, no design verification questions.
What is the difference between using a struct in C and an object in C++?
All the interviewers are Indians and were really nice. I had a really good conversation each interview is about an hour. Everyone had a set of questions prepared and asking me to solve. 1. Full SV - fork join_none, virutal functions, $cast, static variable, Cache size - direct mapping, MESI FSM, constarints, parity check - post randomize 2. STA - hold violations, max freq, FIFO depth, metasibility 3. DUT - muti master muti slave bridge verification - draw the env and testcases, AXI signals 4. UVM - phases, AXI why not APB?, AXI lite vs. AXI 3.0, Driver code, coverage class and do cross coverage. 5. HR -> about team work, resources you used in a project, set back you faced. Explained most employee benefits, applying for H1B and green card, etc
Describe Cache coherence protocols, working of a 5 stage pipeline
Describe the handshake between UVM agent and UVM sequencer
Explain gray code and FIFO techinique?
Viewing 71 - 80 interview questions