FIFO, LIFO in Verilog
Design Verification Interview Questions
1,116 design verification interview questions shared by candidates
Lcm, Swap, Factorial for C coding Write constraints in system verilog
How to have accurate testing when you a large test case to cover.
It gets very technical ranging from Electrical fundamentals to RF fundamentals and then they start to dig deep on each aspect. Know your chip caps really well! I was asked questions on smith charts, imedance matching, typical RF receiver/transmitter systems, signal integrity issues, characteristics of RF amps. As far as behavioral questions were concerned - challenges faced in your last project, how did u solve it and what would your ex boss say about you if I asked him for a reference.
Describe Yourself, project related question.
Where do you see yourself in 5 years?
implement 4-2 priority decoder to 16-4.
1st phone interview: Basics of Verilog. Explanations for different projects on resume. 2D array containing image data, how will you rotate the matrix to rotate the image by 90 degrees clockwise? try to use least memory(i.e) rotate and store in the same input matrix.
Basic RTL Design related concepts, SV UVM basic concepts, writing scoreboard.
Random number generations, assertions, constraints etc.
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