SV, UVM and Digital Electronics Questions.
Design Verification Interview Questions
1,113 design verification interview questions shared by candidates
Uvm phases and explain them
1.timeout function 2.AXi assertions 3.display through command line arguments
what is setup and hold time?
1. Draw the CMOS circuit for NAND gate and explain it's working. 2. Difference between Low pass filter and High pass filter. 3. Frequency response of unit step function. 4. What is sampling and aliasing? 5. Rigorous analysis of testbench code for a given DUT.
Pretty basic digital design questions- timing, logic design etc.. Signal processing questions-sampling, nyquist rate definition, quantization error etc..
Phone Interview with a Design Verification Engineer: Questions on Digital Signal Processing, Analog basics and System Verilog basics.
Asked some questions on C++, constraints, and basic UVM
Read after write sequence implementation
related to projects and your role in the project
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