Questions on interface, clocking blocks, assertions, uvm, X propagation.
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
crazy nonsense questions. How do you measure voltage of the wave from modelsim in gtkwave.? each question on each word in resume.
What is your experience with random constrained stimulus?
show how code coverage and function coverage works. explain with code
APB and AXI protocol explation with all signals.
The asked about past work experience.
Explain about FIFO, Clk generation, State machine
Verilog based questions - circuit was given and then i had to give an optimized code for it.
every details on uvm, some coding question and data structure
Tell me about yourself. Do you mind to relocate?
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