Generate clock using always and forever in verilog
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Screening - shallow copy, deep copy (explain with code), polymorphism, virtual functions and overriding, sizing the dimensions of a multi dimensional array, constraints unique elements in a 2d array, sv events Panel - Constraints to generate unique address, aligned addresses, task for a driver with some conditions given (follow up -> response packet), using fork join for parallel driver, write driver for a dut which has 3 independent request channels and 2 independent response channels, sv code to find a number is multiple of 8, find output of sv snippet with mixed blocking and non blocking, use of $cast to check class type, declare and initialise a dynamic array, add an element to the same array while keeping previous ones as well, what are hazards in pipelined arch., dynamic branch prediction , data forwarding, randc without using rand, covergroup to cover overflow address, explain advantages of uvm over sv, how does a test start and end in uvm, what happens to the simulation if no objections are raised, how would you detect a hang in a test, write a task for time out
Digital design basics, SV, UVM, SVA
Tell me about yourself and then questions on verilog
About Electronic basics and Communcation basics
1. SV constraint 2. UVM 3. Resume review
For the design verification interview, I haven't prepared at all since I didn't know that it was a verification position, all the questions about programing were not answered well.
questions on digital electronics and verilog
Develop a C algorithm to solve arbitration in bus
How instructions are executed in assembly language? How data is transferred between cpu and cache? Why we need cache, why we don't use main memory? Why cache size is kept small?
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