test bench architecture tesplan and verification
Design Verification Engineer Interview Questions
952 design verification engineer interview questions shared by candidates
What do each of the bits represent in a memory address having a two-way associative cache with size: X words, Y lines, etc.
First there was some basic questions on Computer Architecture, Verification Concepts and RESUME. After that she asked me to write code for hamming distance in prefered lang and UVM Code for driver component.
Configdb? Mailboxes etc
1]fabonassi series, 2]binary tree 3]sorting array without built in functions 4]probablities when randomizing 5] unique constraint.
Questions from digital electronics and logical reasoning (Verilog, SV and UVM if u know)
Digital electronics,vhdl, verilog, system verilog
NVME Project How it works?
Q: Can you explain the difference between blocking and non-blocking assignments in SystemVerilog? Q: How would you verify a FIFO design? Q: What is a virtual interface and how do you use it in UVM? Q: How do you handle back-to-back transactions in a UVM sequence? Q: How do you debug a failing assertion in simulation?
what is mailbox why we don't use queue instead of mailbox. what is polymorphism and their uses. what is diff bw trsanction and transfer wrt axi.
Viewing 531 - 540 interview questions