mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
Design Verification Engineer Interview Questions
952 design verification engineer interview questions shared by candidates
Computer Architecture, Logic design, validation, software, behavioral.
functional coverage, types of bins, types of array, constraint examples, virtual class,threads
Digital Logic, Computer Architecture, SystemVerilog, UVM, basic PERl
Questions about debug of failure
Some standard programming questions, hardware and power specific design questions, as well as test philosophy.
Given a 32 bit signal, create a SystemVerilog constraint that ensures that only 2 bits are flipped in randomization.
Give a logic expression to describe the relationship C = A > B
Explain the difference beteween Blocking vs Non-Blocking Assignments.
Typical Scoreboard Structure. What is an Analysis Port?
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