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Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Online interview: 1. What is polymorphism ? 2. Design a 3 bit shift register in verilog RTL ? 3. For a FIFO design, what kind of assertions will you write(what conditions would you check for proper functioning of the FIFO) ?
First interview: describe a FSM for the result of a sequence of binary input mod 5. Merge sort. Second : C/ verilog coding.
Sorting, bit logic
class A; function int foo(); int a; return ++a; endfunction endclass program tb; A a; int b, c; initial begin for(int i = 0; i < 10; i++) begin b = a.foo(); c = foo(); $display("B = %0d", b); $display("C = %0d", c); end end function int foo(); int a; return ++a; endfunction
what is a uvm agent?
Write a scoreboard in SV or UVM for simple alu where there is an 8 bit input that is changing value every clock cycle and the output should be equal to sum of previous 5 inputs.
Tell me a bit about yourself.
Immediate vs. Concurrent Assertions .
What is a pipeline driver?
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